1. Field
Embodiments relate to a semiconductor memory device. More particularly, embodiments relate to a data path circuit of a semiconductor memory device, such as a dynamic random access memory.
2. Description of the Related Art
In recent years, the processing speed and the degree of integration of semiconductor memory devices, such as dynamic random access memories, have been increased to meet user demands. A dynamic random access memory (DRAM) device including one access transistor and one storage capacitor as a unit memory cell is generally used as a main memory of an electronic system.
During the read operation of a DRAM, a bit line sense amplifier may sense and amplify data stored in the memory cells on a pair of bit lines. Then, when a column selection line (hereinafter, referred to as a CSL) signal is activated, the amplified data may be transmitted to a pair of local input/output lines. The data transmitted to the pair of local input/output lines may be transmitted to a data output buffer through a pair of global input/output lines and may then be read to the outside.
In memory devices, e.g., DRAM devices, when lines, e.g., bit lines or local input/output lines, are not active, they are generally precharged to a level to prevent floating and to increase sensing speed. In a general DRAM, e.g., the pre-charge level of the pair of local input/output lines may be equal to a level of the bit line sensing voltage. The bit line sensing voltage is generally the internal power supply voltage of the memory cell array, and the pair of local input/output lines is precharged with the internal power supply voltage. Then, when local line sensing is performed, only one of the pair of local input/output lines may be pulled down to a ground voltage GND unlike a bit line sensing scheme in which the pair of local input/output lines is precharged with a half power supply voltage and is pulled up or pulled down to VDD or GND. Therefore, in the local line sensing scheme, when the optimal voltage level is not used, the amount of current consumed by the local input/output line sense amplifier may be unnecessarily increased, as compared to the bit line sensing scheme. Such unnecessarily higher power consumption reduces performance, e.g., when the DRAM is used for portable electronic devices performance of such portable electronic devices may be reduced.
Typically, when a precharge level for a pair of local input/output lines is not optimized, bit line disturbance is more likely to occur when a pair of bit lines is active. In such cases, charge may be transmitted from the local input/output line to the bit line, which may result in bit line disturbance. As a result, data stored in the memory cell may be reversed.
Therefore, a technique is required which can reduce, minimize, and/or eliminate bit line disturbance, reduce power consumption, and achieve a low-voltage and high-speed operation in a data path circuit of a DRAM that transmits data read from memory cells to an output buffer.